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1/49 april 2001 m59mr032c m59mr032d 32 mbit (2mb x16, mux i/o, dual bank, burst) 1.8v supply flash memory n supply voltage Cv dd = v ddq = 1.65v to 2.0v for program, erase and read Cv pp = 12v for fast program (optional) n multiplexed address/data n synchronous / asynchronous read C configurable burst mode read C page mode read (4 words page) C random access: 100ns n programming time C 10s by word typical C double word programming option n memory blocks C dual bank memory array: 8 mbit - 24 mbit C parameter blocks (top or bottom location) n dual bank operations C read within one bank while program or erase within the other C no delay between read and write operations n block protection/unprotection C all blocks protected at power-up C any combination of blocks can be protected n common flash interface (cfi) n 64 bit security code n erase suspend and resume modes n 100,000 program/erase cycles per block n electronic signature C manufacturer code: 20h C top device code, m59mr032c: a4h C bottom device code, m59mr032d: a5h bga m bga lfbga54 (zc) 10 x 4 ball array bga46 (gc) 10 x 4 ball array figure 1. logic diagram ai90109 5 a16-a20 w adq0-adq15 v dd m59mr032c m59mr032d e v ss 16 g rp wp v ddq v pp l k wait binv
m59mr032c, m59mr032d 2/49 figure 2. lfbga connections (top view through package) ai90110 v ddq adq10 adq11 adq4 adq5 v ss adq14 adq15 h adq9 adq2 adq3 adq6 adq7 v ss g a18 wp rp binv l a20 a16 v ddq f a19 v pp w v dd k wait e 8 7 6 5 4 3 2 1 adq1 adq8 e a17 adq0 g 10 9 adq13 adq12 v ss v ss du du du du du du du du du du du du du du du d c b a m l k j du
3/49 m59mr032c, m59mr032d figure 3. bga connections (top view through package) ai90111 v ddq adq10 adq11 adq4 adq5 v ss adq14 adq15 h adq9 adq2 adq3 adq6 adq7 v ss g a18 wp rp binv l a20 a16 v ddq f a19 v pp w v dd k wait e 8 7 6 5 4 3 2 1 adq1 adq8 e a17 adq0 g 10 9 adq13 adq12 v ss v ss d c b a du du du du 12 11 du du du du 14 13
m59mr032c, m59mr032d 4/49 table 1. signal names a16-a20 address inputs adq0-adq15 data input/outputs or address inputs, command inputs e chip enable g output enable w write enable rp reset/power-down wp write protect k burst clock l latch enable wait wait data in burst mode binv bus invert v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground du dont use as internally connected description the m59mr032 is a 32 mbit non-volatile flash memory that may be erased electrically at block level and programmed in-system on a word-by- word basis using a 1.65v to 2.0v v dd supply for the circuitry. for program and erase operations the necessary high voltages are generated inter- nally. the device supports synchronous burst read and asynchronous page mode read from all the blocks of the memory array; at power-up the de- vice is configured for page mode read. in synchro- nous burst mode, a new data is output at each clock cycle for frequencies up to 54mhz. the array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. all blocks are protected against pro- gramming and erase at power-up. blocks can be unprotected to make changes in the application and then reprotected. instructions for read/reset, auto select, write configuration register, programming, block erase, bank erase, erase suspend, erase re- sume, block protect, block unprotect, block lock- ing, cfi query, are written to the memory through a command interface (c.i.) using standard micro- processor write timings. the memory is offered in lfbga54 and bga46, 0.5 mm ball pitch packages and it is supplied with all the bits erased (set to 1). table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition s above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. depends on range. 3. minimum voltage may undershoot to C2v during transition and for less than 20ns. symbol parameter value unit t a ambient operating temperature (2) C40 to 85 c t bias temperature under bias C40 to 125 c t stg storage temperature C55 to 155 c v io (3) input or output voltage C0.5 to v ddq +0.5 v v dd , v ddq supply voltage C0.5 to 2.7 v v pp program voltage C0.5 to 13 v
5/49 m59mr032c, m59mr032d organization the m59mr032 is organized as 2mbit by 16 bits. the first sixteen address lines are multiplexed with the data input/output signals on the multiplexed address/data bus adq0-adq15. the remaining address lines a16-a20 are the msb addresses. memory control is provided by chip enable e , out- put enable g and write enable w inputs. the clock k input synchronizes the memory to the microprocessor during burst read. reset rp is used to reset all the memory circuitry and to set the chip in power-down mode if this function is enabled by a proper setting of the con- figuration register. erase and program operations are controlled by an internal program/erase con- troller (p/e.c.). status register data output on adq7 provides a data polling signal, adq6 and adq2 provide toggle signals and adq5 provides error bit to indicate the state of the p/e.c opera- tions. wait output indicates to the microprocessor the status of the memory during the burst mode operations. memory blocks the device features asymmetrically blocked archi- tecture. m59mr032 has an array of 71 blocks and is divided into two banks a and b, providing dual bank operations. while programming or erasing in bank a, read operations are possible into bank b or vice versa. the memory also features an erase suspend allowing to read or program in another block within the same bank. once suspended the erase can be resumed. the bank size and sector- ization are summarized in table 8. parameter blocks are located at the top of the memory ad- dress space for the m59mr032c, and at the bot- tom for the m59mr032d. the memory maps are shown in tables 4, 5, 6 and 7. the program and erase operations are managed automatically by the p/e.c. block protection against program or erase provides additional data security. instructions are provided to protect or un- protect any block in the application. a second reg- ister locks the protection status while wp is low (see block locking description). all blocks are pro- tected and unlocked at power-up. table 3. bank size and sectorization bank size parameter blocks main blocks bank a 8 mbit 8 blocks of 4 kword 15 blocks of 32 kword bank b 24 mbit - 48 blocks of 32 kword
m59mr032c, m59mr032d 6/49 table 4. bank a, top boot block addresses m59mr032c table 5. bank b, top boot block addresses m59mr032c # size (kword) address range 22 4 1ff000h-1fffffh 21 4 1fe000h-1fefffh 20 4 1fd000h-1fdfffh 19 4 1fc000h-1fcfffh 18 4 1fb000h-1fbfffh 17 4 1fa000h-1fafffh 16 4 1f9000h-1f9fffh 15 4 1f8000h-1f8fffh 14 32 1f0000h-1f7fffh 13 32 1e8000h-1effffh 12 32 1e0000h-1e7fffh 11 32 1d8000h-1dffffh 10 32 1d0000h-1d7fffh 9 32 1c8000h-1cffffh 8 32 1c0000h-1c7fffh 7 32 1b8000h-1bffffh 6 32 1b0000h-1b7fffh 5 32 1a8000h-1affffh 4 32 1a0000h-1a7fffh 3 32 198000h-19ffffh 2 32 190000h-197fffh 1 32 188000h-18ffffh 0 32 180000h-187fffh # size (kword) address range 47 32 178000h-17ffffh 46 32 170000h-177fffh 45 32 168000h-16ffffh 44 32 160000h-167fffh 43 32 158000h-15ffffh 42 32 150000h-157fffh 41 32 148000h-14ffffh 40 32 140000h-147fffh 39 32 138000h-13ffffh 38 32 130000h-137fffh 37 32 128000h-12ffffh 36 32 120000h-127fffh 35 32 118000h-11ffffh 34 32 110000h-117fffh 33 32 108000h-10ffffh 32 32 100000h-107fffh 31 32 0f8000h-0fffffh 30 32 0f0000h-0f7fffh 29 32 0e8000h-0effffh 28 32 0e0000h-0e7fffh 27 32 0d8000h-0dffffh 26 32 0d0000h-0d7fffh 25 32 0c8000h-0cffffh 24 32 0c0000h-0c7fffh 23 32 0b8000h-0bffffh 22 32 0b0000h-0b7fffh 21 32 0a8000h-0affffh 20 32 0a0000h-0a7fffh 19 32 098000h-09ffffh 18 32 090000h-097fffh 17 32 088000h-08ffffh 16 32 080000h-087fffh 15 32 078000h-07ffffh 14 32 070000h-077fffh 13 32 068000h-06ffffh 12 32 060000h-067fffh 11 32 058000h-05ffffh 10 32 050000h-057fffh 9 32 048000h-04ffffh 8 32 040000h-047fffh 7 32 038000h-03ffffh 6 32 030000h-037fffh 5 32 028000h-02ffffh 4 32 020000h-027fffh 3 32 018000h-01ffffh 2 32 010000h-017fffh 1 32 008000h-00ffffh 0 32 000000h-007fffh
7/49 m59mr032c, m59mr032d table 6. bank b, bottom boot block addresses m59mr032d # size (kword) address range 47 32 1f8000h-1fffffh 46 32 1f0000h-1f7fffh 45 32 1e8000h-1effffh 44 32 1e0000h-1e7fffh 43 32 1d8000h-1dffffh 42 32 1d0000h-1d7fffh 41 32 1c8000h-1cffffh 40 32 1c0000h-1c7fffh 39 32 1b8000h-1bffffh 38 32 1b0000h-1b7fffh 37 32 1a8000h-1affffh 36 32 1a0000h-1a7fffh 35 32 198000h-19ffffh 34 32 190000h-197fffh 33 32 188000h-18ffffh 32 32 180000h-187fffh 31 32 178000h-17ffffh 30 32 170000h-177fffh 29 32 168000h-16ffffh 28 32 160000h-167fffh 27 32 158000h-15ffffh 26 32 150000h-157fffh 25 32 148000h-14ffffh 24 32 140000h-147fffh 23 32 138000h-13ffffh 22 32 130000h-137fffh 21 32 128000h-12ffffh 20 32 120000h-127fffh 19 32 118000h-11ffffh 18 32 110000h-117fffh 17 32 108000h-10ffffh 16 32 100000h-107fffh 15 32 0f8000h-0fffffh 14 32 0f0000h-0f7fffh 13 32 0e8000h-0effffh 12 32 0e0000h-0e7fffh table 7. bank a, bottom boot block addresses m59mr032d 11 32 0d8000h-0dffffh 10 32 0d0000h-0d7fffh 9 32 0c8000h-0cffffh 8 32 0c0000h-0c7fffh 7 32 0b8000h-0bffffh 6 32 0b0000h-0b7fffh 5 32 0a8000h-0affffh 4 32 0a0000h-0a7fffh 3 32 098000h-09ffffh 2 32 090000h-097fffh 1 32 088000h-08ffffh 0 32 080000h-087fffh # size (kword) address range 22 32 078000h-07ffffh 21 32 070000h-077fffh 20 32 068000h-06ffffh 19 32 060000h-067fffh 18 32 058000h-05ffffh 17 32 050000h-057fffh 16 32 048000h-04ffffh 15 32 040000h-047fffh 14 32 038000h-03ffffh 13 32 030000h-037fffh 12 32 028000h-02ffffh 11 32 020000h-027fffh 10 32 018000h-01ffffh 9 32 010000h-017fffh 8 32 008000h-00ffffh 7 4 007000h-007fffh 6 4 006000h-006fffh 5 4 005000h-005fffh 4 4 004000h-004fffh 3 4 003000h-003fffh 2 4 002000h-002fffh 1 4 001000h-001fffh 0 4 000000h-000fffh
m59mr032c, m59mr032d 8/49 signal descriptions see figure 1 and table 1. address inputs or data input/output (adq0- adq15). when chip enable e is at v il and out- put enable g is at v ih the multiplexed address/ data bus is used to input addresses for the memo- ry array, data to be programmed in the memory ar- ray or commands to be written to the c.i. the address inputs for the memory array are latched on the rising edge of latch enable l . the address latch is transparent when l is at v il . both input data and commands are latched on the rising edge of write enable w . when chip enable e and out- put enable g are at v il the address/data bus out- puts data from the memory array, the electronic signature manufacturer or device codes, the block protection status the configuration register status or the status register data polling bit adq7, the toggle bits adq6 and adq2, the error bit adq5. the address/data bus is high imped- ance when the chip is deselected, output enable g is at v ih , or rp is at v il . address inputs (a16-a20). the five msb ad- dresses of the memory array are latched on the rising edge of latch enable l . chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. e at v ih deselects the memory and reduces the power consumption to the standby level. e can also be used to control writing to the command register and to the memo- ry array, while w remains at v il . output enable (g ). the output enable gates the outputs through the data buffers during a read op- eration. when g is at v ih the outputs are high im- pedance. write enable (w ). this input controls writing to the command register and data latches. data are latched on the rising edge of w . write protect (wp ). this input gives an addition- al hardware protection level against program or erase when pulled at v il , as described in the block lock instruction description. reset/power-down input (rp ). the rp input provides hardware reset of the memory, and/or power-down functions, depending on the configu- ration register status. reset/power-down of the memory is achieved by pulling rp to v il for at least t plph . when the reset pulse is given, if the memory is in read, erase suspend read or standby, it will output new valid data in t phq7v1 af- ter the rising edge of rp . if the memory is in erase or program modes, the operation will be aborted and the reset recovery will take a maximum of t plq7v . the memory will recover from power- down (when enabled) in t phq7v2 after the rising edge of rp . exit from reset/power-down changes the contents of the configuration register bits 14 and 15, setting the memory in asynchronous page mode read and power save function disabled. all blocks are protected and unlocked after a reset/ power-down. see tables 29, 31 and figure 14. latch enable (l ). l latches the address bits adq0-adq15 and a16-a20 on its rising edge. the address latch is transparent when l is at v il and it is inhibited when l is at v ih . clock (k). the clock input synchronizes the memory to the microcontroller during burst mode read operation; the address is latched on a k edge (rising or falling, according to the configuration set- tings) when l is at v il . k is dont care during asyn- chronous page mode read and in write operations. wait (wait ). wait is an output signal used dur- ing burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. this output is high impedance when e or g are high or rp is at v il , and can be configured to be active during the wait cycle or one clock cy- cle in advance.
9/49 m59mr032c, m59mr032d bus invert (binv). binv is an input/output signal used to reduce the amount of power needed to switch the external address/data bus. the power saving is achieved by inverting the data output on adq0-adq15 every time this gives an advantage in terms of number of toggling bits. in burst mode read, each new data output from the memory is compared with the previous data. if the number of transitions required on the data bus is in excess of 8, the data is inverted and the binv signal will be driven by the memory at v oh to inform the receiv- ing system that data must be inverted before any further processing. by doing so, the actual transi- tions on the data bus will be less than 8. in a simi- lar way, when a command is given, binv may be driven by the system at v ih to inform the memory that the data must be inverted.like the other input/ output pins, binv is high impedance when the chip is deselected, output enable g is at v ih or rp is at v il ; when used as an input, binv must follow the same setup and hold timings of the data in- puts. v dd and v ddq supply voltage (1.65v to 2.0v). the main power supply for all operations (read, program and erase). v dd and v ddq must be at the same voltage. v pp program supply voltage (12v). v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin; if v pp is kept in a low voltage range (0 to 2v) v pp is seen as a control input, and the current absorption is limited to 5a (0.2a typ- ical). in this case with v pp = v il we obtain an ab- solute protection against program or erase; with v pp = v pp1 these functions are enabled. v pp val- ue is only sampled during program or erase write cycles; a change in its value after the operation has been started does not have any effect and program or erase are carried on regularly. if v pp is used in the 11.4v to 12.6v range (v pp2 ) then the pin acts as a power supply. this supply voltage must remain stable as long as program or erase are finished. in read mode the current sunk is less then 0.5ma, while during program and erase oper- ations the current may increase up to 10ma. v ss ground. v ss is the reference for all the volt- age measurements.
m59mr032c, m59mr032d 10/49 table 8. user bus operations (1) note: 1. x = don't care. table 9. read electronic signature (as and read cfi instructions) (1) note: 1. addresses are latched on the rising edge of l input. table 10. read block protection (as and read cfi instructions) (1) note: 1. addresses are latched on the rising edge of l input. 2. a locked block can be unprotected only with wp at v ih. operation e g w rp wp adq0-adq15 write v il v ih v il v ih v ih data input output disable v il v ih v ih v ih v ih hi-z standby v ih xx v ih v ih hi-z reset / power-down x x x v il v ih hi-z block locking v il xx v ih v il x code device e g w a0-a7 a8-a20 data manufacturer code v il v il v ih 00h don't care 0020h device code m59mr032c v il v il v ih 01h don't care 00a4h m59mr032d v il v il v ih 01h don't care 00a5h block status e g w a0-a7 a8-a11 a12-a20 data protected and unlocked v il v il v ih 02h don't care block address 0001 unprotected and unlocked v il v il v ih 02h don't care block address 0000 protected and locked v il v il v ih 02h don't care block address 0003 unprotected and locked (2) v il v il v ih 02h don't care block address 0002 device operations the following operations can be performed using the appropriate bus cycles: address latch, read array (random, and page modes), write com- mand, output disable, standby, reset/power- down and block locking. see table 8. address latch. in asynchronous operation, the address is latched on the rising edge of l input; in burst mode, the address is latched either by l go- ing high or with a rising/falling edge of k, depend- ing on the clock configuration. read. read operations are used to output the contents of the memory array, the electronic sig- nature, the status register, the cfi, the block protection status, the configuration register sta- tus and the security code. read operation of the memory array may be per- formed in asynchronous page mode or synchro- nous burst mode. in asynchronous page mode data is internally read and stored in a page buffer. the page has a size of 4 words and is addressed by adq0 and adq1 address inputs. according to the device configuration the following read operations: electronic signature - status register - cfi - block protection status - configu- ration register status - security code must be ac- cessed as asynchronous read or as single synchronous burst mode (see figure 4). both chip enable e and output enable g must be at v il in order to read the output of the memory.
11/49 m59mr032c, m59mr032d figure 4. read operation sequence when cr15 = 0 (excluding read memory array) ai90112 a16-a20 valid address k l adq0-adq15 valid address valid data not valid adq0-adq15 valid address valid data adq0-adq15 valid address valid data not valid not valid configuration code 6 configuration code 3 conf. code 2 burst read. the device also supports a burst read. in this mode, an address is first latched on the rising edge of l or k (or falling edge of k, ac- cording to configuration settings); after a config- urable delay of 2 to 6 clock cycles a new data is output at each clock cycle. the burst sequence may be configured for linear or interleaved order and for a length of 4, 8 words or for continuous burst mode. a wait signal may be asserted to indicate to the system that an output delay will occur. this delay will depend on the starting address of the burst sequence; the worst case delay will oc- cur when the sequence is crossing a 32 word boundary and the starting address was at the end of a four word boundary. see the write configura- tion register (cr) instruction for more details on all the possible settings for the synchronous burst read. write. write operations are used to give instruc- tion commands to the memory or to latch input data to be programmed. a write operation is initi- ated when chip enable e and write enable w are at v il with output enable g at v ih . addresses are latched on the rising edge of l . commands and in- put data are latched on the rising edge of w or e whichever occurs first. noise pulses of less than 5ns typical on e , w and g signals do not start a write cycle. write operations are asynchronous and clock is ignored during write. dual bank operations. the dual bank allows to read data from one bank of memory while a pro- gram or erase operation is in progress in the other bank of the memory. read and write cycles can be initiated for simultaneous operations in different banks without any delay. status register during program or erase must be monitored using an ad- dress within the bank being modified. output disable. the data outputs are high im- pedance when the output enable g is at v ih with write enable w at v ih . standby. the memory is in standby when chip enable e is at v ih and the p/e.c. is idle. the pow- er consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable g or write enable w inputs. automatic standby. when in read mode, after 150ns of bus inactivity and when cmos levels are driving the addresses, the chip automatically en- ters a pseudo-standby mode where consumption is reduced to the cmos standby value, while out- puts still drive the bus. the automatic standby fea- ture is not available when the device is configured for synchronous burst mode. power-down. the memory is in power-down when the configuration register is set for power- down and rp is at v il . the power consumption is reduced to the power-down level, and outputs are in high impedance, independent of the chip en- able e , output enable g or write enable w inputs. block locking. any combination of blocks can be temporarily protected against program or erase by setting the lock register and pulling wp to v il (see block lock instruction).
m59mr032c, m59mr032d 12/49 instructions and commands seventeen instructions are defined (see table 17), and the internal p/e.c. automatically handles all timing and verification of the program and erase operations. the status register data poll- ing, toggle, error bits can be read at any time, dur- ing programming or erase, to monitor the progress of the operation. instructions, made up of one or more commands written in cycles, can be given to the program/ erase controller through a command interface (c.i.). the c.i. latches commands written to the memory. commands are made of address and data sequences. two coded cycles unlock the command interface. they are followed by an input command or a confirmation command. the coded sequence consists of writing the data aah at the address 555h during the first cycle and the data 55h at the address 2aah during the second cycle. instructions are composed of up to six cycles. the first two cycles input a coded sequence to the command interface which is common to all in- structions (see table 17). the third cycle inputs the instruction set-up command. subsequent cy- cles output the addressed data, electronic signa- ture, block protection, configuration register status or cfi query for read operations. in order to give additional data protection, the instructions for block erase and bank erase require further command inputs. for a program instruction, the fourth command cycle inputs the address and data to be programmed. for a double word program- ming instruction, the fourth and fifth command cy- cles input the address and data to be programmed. for a block erase and bank erase instructions, the fourth and fifth cycles input a fur- ther coded sequence before the erase confirm command on the sixth cycle. any combination of blocks of the same memory bank can be erased. erasure of a memory block may be suspended, in order to read data from another block or to pro- gram data in another block, and then resumed. when power is first applied the command interface is reset to read array. command sequencing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycles has been chosen to ensure maximum data security. read/reset (rd) instruction. the read/reset instruction consists of one write cycle giving the command f0h. it can be optionally preceded by the two coded cycles. subsequent read opera- tions will read the memory array addressed and output the data read. the reset command does not affect the configuration of unprotected blocks and the configuration register status. read/re- set instruction is ignored when program or erase is in progress. cfi query (rcfi) instruction. common flash interface query mode is entered writing 98h at ad- dress 55h. the cfi data structure gives informa- tion on the device, such as the sectorization, the command set and some electrical specifications. tables 19, 20, 21 and 22 show the addresses used to retrieve each data. the cfi data structure contains also a security area; in this section, a 64 bit unique security number, organized by word, is written starting at address 81h. this area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by st. write a read instruction (rd) to return to read array mode. table 11. commands hex code command 00h bypass reset 10h bank erase confirm 20h unlock bypass 30h block erase resume/confirm 40h double word program 60h block protect, or block unprotect, or block lock, or write configuration register 80h set-up erase 90h read electronic signature, or block protection status, or configuration register status 98h cfi query a0h program b0h erase suspend f0h read array/reset
13/49 m59mr032c, m59mr032d auto select (as) instruction. this instruc- tion uses two coded cycles followed by one write cycle giving the command 90h to address 555h for command set-up. a subsequent read will output the manufacturer or the device code (electronic signature), the block protection status or the con- figuration register status depending on the levels of adq0 and adq1 (see tables 9, 10 and 11). the electronic signature can be read from the memory allowing programming equipment or ap- plications to automatically match their interface to the characteristics of m59mr032. the manufac- turer code is output when the address lines adq0 and adq1 are at v il , the device code is output when adq0 is at v ih with adq1 at v il . the codes are output on adq0-adq7 with adq8- adq15 at 00h. the as instruction also allows the access to the block protection status. after giving the as instruction, adq0 is set to v il with adq1 at v ih , while a12-a20 define the address of the block to be verified (see table 10). the as instruc- tion finally allows the access to the configuration register status if both adq0 and adq1 are set to v ih ; refer to table 12 for configuration register de- scription. a reset command puts the device in read array mode. write configuration register (cr) instruc- tion. this instruction uses two coded cycles fol- lowed by one write cycle giving the command 60h to address 555h. a further write cycle giving the command 03h writes the contents of address bits adq0-adq15 to bits cr15-cr0 of the configura- tion register. at power-up the configuration reg- ister is set to asynchronous read mode, power- down disabled and bus invert (power save func- tion) disabled. a description of the effects of each configuration bit is given in table 12. table 12. read configuration register (as and read cfi instructions) configuration register function cr15 read mode 0 = burst mode read 1 = page mode read (default) cr14 bus invert configuration (power save) 0 = disabled (default) 1 = enabled cr13-cr11 x-latency 010 = 2 clock latency 011 = 3 clock latency 100 = 4 clock latency 101 = 5 clock latency 110 = 6 clock latency cr10 power-down configuration 0 = power-down disabled (default) 1 = power-down enabled cr9 data hold configuration 0 = data output at every clock cycle 1 = data output every 2 clock cycles cr8 wait configuration 0 = wait is active during wait state 1 = wait is active one data cycle before wait state cr7 burst order configuration 0 = interleaved 1 = linear cr6 clock configuration 0 = address latched and data output on the falling clock edge. 1 = address latched and data output on the rising clock edge. cr5-cr3 reserved cr2-cr0 burst length 001 = 4 word burst length 010 = 8 word burst length 111 = continuous burst mode (requires cr7 = 1)
m59mr032c, m59mr032d 14/49 table 13. x-latency configuration note: 1. configuration codes 5 and 6 may be used only in conjunction with configuration bit cr9 set at 1 (one data every 2 clock cycle s). configuration code input frequency 100ns 120ns 2 25mhz 20mhz 3 40mhz 30mhz 4 54mhz 40mhz 5 (1) 66mhz 50mhz 6 (1) C 60mhz figure 5. x-latency configuration sequence ai90113 a16-a20 valid address k l adq0-adq15 valid address valid data valid data adq0-adq15 valid address valid data adq0-adq15 valid address valid data valid data valid data configuration code 6 configuration code 3 conf. code 2 C read mode (cr15). the device supports an asynchronous page mode and a synchronous burst mode. in asynchronous page mode, the default at power-up, data is internally read and stored in a buffer of 4 words selected by adq0 and adq1 address inputs. in synchronous burst mode, the device latches the starting address and then outputs a sequence of data which de- pends on the configuration register settings. C bus invert configuration (cr14). this regis- ter bit is used to enable the binv pin functional- ity. binv functionality depends upon configuration bits cr14 and cr15 (see table 12 for configuration bits definition) as shown in table 14. as output pin binv is active only when enabled (cr14 = 1) in read array burst mode (cr15 = 0). as input pin binv is active only when enabled (cr14 = 1). binv is ignored when adq0- adq15 lines are used as address inputs (ad- dresses must not be inverted). table 14. binv configuration bits cr15 cr14 binv in out 00x0 0 1 active active 10x0 1 1 active 0
15/49 m59mr032c, m59mr032d C x-latency (cr13-cr11). these configuration bits define the number of clock cycles elapsing from l going low to valid data available in burst mode. the correspondence between x-latency settings and the sustainable clock frequencies is given in table 13 and figure 5. C power-down configuration (cr10). the rp pin may be configured to give a very low power consumption when driven low (power-down state). in power-down the i cc supply current is reduced to a typical figure of 2a; if this function is disabled (default at power-up) the rp pin causes only a reset of the device and the supply current is the stand-by value. the recovery time after a rp pulse is significantly longer (50s vs. 150ns) when power-down is enabled. C data hold configuration (cr9). in burst mode this register bit determines if a new data is output at each clock cycle or every 2 clock cy- cles. C wait configuration (cr8). in burst mode wait indicates whether the data on the output bus are valid or a wait state must be inserted. the configuration bit determines if wait will be asserted one clock cycle before the wait state or during the wait state (see figure 10). C burst order configuration (cr7). see table 15 for burst order and length. C clock configuration (cr6). in burst mode de- termines if address is latched and data is output on the rising or falling edge of the clock. C burst length (cr2-cr0). in burst mode deter- mines the number of words output by the mem- ory. it is possible to have 4 words, 8 words or a table 15. burst order and length configuration starting address 4 words 8 words continuous burst linear interleaved linear interleaved 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6... 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8... ... 7 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11... ... 28 28-29-30-31-32... 29 29-30-31-wait-32... 30 30-31-wait-wait-32... 31 31-wait-wait-wait-32... continuous burst mode, in which all the words in bank a or bank b are read sequentially. in con- tinuous burst mode the burst sequence is inter- rupted at the end of each of the two banks or when a suspended block is reached. in continu- ous burst mode it may happen that the memory will stop the data output flow for a few clock cy- cles; this event is signaled by wait going low until the output flow is resumed. the initial ad- dress determines if the output delay will occur as well as its duration. if the starting address is aligned to a four word boundary no wait states will be needed. if the starting address is shifted by 1,2 or 3 positions from the four word bound- ary, wait will be asserted for 1,2 or 3 clock cy- cles (2,4, 6 cycles if cr9 is set at 1) when the burst sequence is crossing the first 32 word boundary. wait will be asserted only once dur- ing a continuous burst access. see also table 15. enter bypass mode (eby) instruction. this in- struction uses the two coded cycles followed by one write cycle giving the command 20h to ad- dress 555h for mode set-up. once in bypass mode, the device will accept the exit bypass (xby) and program or double word program in bypass mode (pgby, dpgby) commands. the bypass mode allows to reduce the overall pro- gramming time when large memory arrays need to be programmed. exit bypass mode (xby) instruction. this in- struction uses two write cycles. the first inputs to the memory the command 90h and the second in- puts the exit bypass mode confirm (00h). after the xby instruction, the device resets to read memo- ry array mode.
m59mr032c, m59mr032d 16/49 program in bypass mode (pgby) instruc- tion. this instruction uses two write cycles. the program command a0h is written to any address on the first cycle and the second write cycle latch- es the address on the rising edge of l and the data to be written on the rising edge of w and starts the p/e.c. read operations within the same bank output the status register bits after the pro- gramming has started. memory programming is made only by writing '0' in place of '1'. the content of the memory cell is not changed if the user write '1' in place of '0' and no error occurs. status bits adq6 and adq7 determine if programming is on- going and adq5 allows verification of any possible error. program (pg) instruction. this instruction uses four write cycles. the program command a0h is written to address 555h on the third cycle after two coded cycles. a fourth write operation latches the address and the data to be written and starts the p/e.c. read operations within the same bank out- put the status register bits after the programming has started. memory programming is made only by writing '0' in place of '1'. the content of the memory cell is not changed if the user write '1' in place of '0' and no error occurs. status bits adq6 and adq7 determine if programming is on-going and adq5 allows verification of any possible error. programming at an address not in blocks being erased is also possible during erase suspend. double word program (dpg) instruction. this feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. high voltage (11.4v to 12.6v) on v pp pin is required. this instruction uses five write cy- cles. the double word program command 40h is written to address 555h on the third cycle after two coded cycles. a fourth write cycle latches the ad- dress and data to be written to the first location. a fifth write cycle latches the new data to be written to the second location and starts the p/e.c.. note that the two locations must have the same address except for the address bit a0. the double word program can be executed in bypass mode (dpg- by) to skip the two coded cycles at the beginning of each command. block protect (bp), block unprotect (bu), block lock (bl) instructions. all blocks are protected and unlocked at power-up. each block of the array has two levels of protection against program or erase operation. the first level is set by the block protect instruction; a protected block cannot be programmed or erased until a block un- protect instruction is given for that block. a second level of protection is set by the block lock instruc- tion, and requires the use of the wp pin, according to the following scheme: C when wp is at v ih , the lock status is overridden and all blocks can be protected or unprotected; C when wp is at v il , lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. blocks that are not locked can still change their protection status, and pro- gram or erase accordingly; table 16. protection states (1) note: 1. all blocks are protected at power-up, so the default configuration is 001 or 101 according to wp status. 2. current state and next state gives the protection status of a block. the protection status is defined by the write protect pi n and by adq1 (= 1 for a locked block) and adq0 (= 1 for a protected block) as read in the autoselect instruction with a1 = v ih and a0 = v il . 3. next state is the protection status of a block after a protect or unprotect or lock command has been issued or after wp has changed its logic value. 4. a wp transition to v ih on a locked block will restore the previous adq0 value, giving a 111 or 110. current state (2) (wp , adq1, adq0) program/erase allowed next state after event (3) protect unprotect lock wp transition 100 yes 101 100 111 000 101 no 101 100 111 001 110 yes 111 110 111 011 111 no 111 110 111 011 000 yes 001 000 011 100 001 no 001 000 011 101 011 no 011 011 011 111 or 110 (4)
17/49 m59mr032c, m59mr032d C the lock status is cleared for all blocks at power- up or pulling rp at v il for at least t plph . the protection and lock status can be monitored for each block using the autoselect (as) instruc- tion. protected blocks will output a 1 on adq0 and locked blocks w ill output a 1 on adq1. after a pulse of rp of at least t plph all blocks are protected and unlocked. refer to table 16 for a list of the protection states. block erase (be) instruction. this instruction uses a minimum of six write cycles. the erase set-up command 80h is written to address 555h on third cycle after the two coded cycles. the block erase confirm command 30h is similarly written on the sixth cycle after another two coded cycles and an address within the block to be erased is given and latched into the memory. additional block erase confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further cod- ed cycles. all blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. the erase will start after an erase timeout period of 100s. thus, additional erase confirm commands for other blocks must be given within this delay. the input of a new erase confirm command will restart the timeout period. the status of the inter- nal timer can be monitored through the level of adq3, if adq3 is '0' the block erase command has been given and the timeout is running, if adq3 is '1', the timeout has expired and the p/ e.c. is erasing the block(s). if the second com- mand given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to read array. it is not necessary to program the block with 00h as the p/e.c. will do this automatically before erasing to ffh. read op- erations within the same bank, after the sixth rising edge of w or e , output the status register bits. during the execution of the erase by the p/e.c., the memory accepts only the erase suspend es instruction; the read/reset rd instruction is ac- cepted during the 100s time-out period. data polling bit adq7 returns '0' while the erasure is in progress and '1' when it has completed. the tog- gle bit adq6 toggles during the erase operation, and stops when erase is completed. after completion the status register bit adq5 re- turns '1' if there has been an erase failure. in such a situation, the toggle bit adq2 can be used to determine which block is not correctly erased. in the case of erase failure, a read/reset rd in- struction is necessary in order to reset the p/e.c. bank erase (bke) instruction. this instruction uses six write cycles and is used to erase all the blocks belonging to the selected bank. the erase set-up command 80h is written to address 555h on the third cycle after the two coded cycles. the bank erase confirm command 10h is similarly written on the sixth cycle after another two coded cycles at an address within the selected bank. if the second command given is not an erase con- firm or if the coded cycles are wrong, the instruc- tion aborts and the device is reset to read array. it is not necessary to program the array with 00h first as the p/e.c. will automatically do this before erasing it to ffh. read operations within the same bank after the sixth rising edge of w or e output the status register bits. during the execution of the erase by the p/e.c., data polling bit adq7 re- turns '0', then '1' on completion. the toggle bit adq6 toggles during erase operation and stops when erase is completed. after completion the status register bit adq5 returns '1' if there has been an erase failure. erase suspend (es) instruction. in a dual bank memory the erase suspend instruction is used to read data within the bank where erase is in progress. it is also possible to program data in blocks not being erased. the erase suspend instruction consists of writing the command b0h without any specific address. no coded cycles are required. erase suspend is accepted only during the block erase instruction execution. the toggle bit adq6 stops toggling when the p/e.c. is suspended within 15s after the erase suspend (es) command has been writ- ten. the device will then automatically be set to read memory array mode. when erase is sus- pended, a read from blocks being erased will out- put adq2 toggling and adq6 at '1'. a read from a block not being erased returns valid data. during suspension the memory will respond only to the erase resume er and the program pg instruc- tions. a program operation can be initiated during erase suspend in one of the blocks not being erased. it will result in adq6 toggling when the data is being programmed. erase resume (er) instruction. if an erase suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at an address within the bank be- ing erased and without any coded cycle.
m59mr032c, m59mr032d 18/49 table 17. instructions (1,2) mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. rd (4) read/reset memory array 1+ addr. (3) x read memory array until a new write cycle is initiated. data f0h 3+ addr. 555h 2aah 555h read memory array until a new write cycle is initiated. data aah 55h f0h rcfi cfi query 1+ addr. 55h read cfi data until a new write cycle is initiated. data 98h as (4) auto select 3+ addr. 555h 2aah 555h read electronic signature or block protection or configuration register status until a new cycle is initiated. data aah 55h 90h cr configuration register write 4 addr. 555h 2aah 555h configura- tion data data aah 55h 60h 03h pg program 4 addr. 555h 2aah 555h program address read data polling or toggle bit until program completes. data aah 55h a0h program data dpg double word program 5 addr. 555h 2aah 555h program address 1 program address 2 note 6, 7 data aah 55h 40h program data 1 program data 2 eby enter bypass mode 3 addr. 555h 2aah 555h data aah 55h 20h xby exit bypass mode 2 addr. xx data 90h 00h pgby program in bypass mode 2 addr. x program address read data polling or toggle bit until program completes. data a0h program data dpgby double word program in bypass mode 3 addr. x program address 1 program address 2 note 6, 7 data 40h program data 1 program data 2 bp block protect 4 addr. 555h 2aah 555h block address data aah 55h 60h 01h bu block unprotect 1 addr. 555h 2aah 555h block address data aah 55h 60h d0h
19/49 m59mr032c, m59mr032d note: 1. commands not interpreted in this table will default to read array mode. 2. for coded cycles address inputs a11-a20 are don't care. 3. x = don't care. 4. the first cycles of the rd or as instructions are followed by read operations. any number of read cycles can occur after the com- mand cycles. 5. during erase suspend, read and data program functions are allowed in blocks not being erased. 6. program address 1 and program address 2 must be consecutive addresses differing only for address bit a0. 7. high voltage on v pp (11.4v to 12.6v) is required for the proper execution of the double word program instruction. bl block lock 4 addr. 555h 2aah 555h block address data aah 55h 60h 2fh be block erase 6+ addr. 555h 2aah 555h 555h 2aah block address data aah 55h 80h aah 55h 30h bke bank erase 6 addr. 555h 2aah 555h 555h 2aah bank address data aah 55h 80h aah 55h 10h es erase suspend 1 addr. (3) x read until toggle stops, then read all the data needed from any blocks not being erased then resume erase. data b0h er erase resume 1 addr. bank address read data polling or toggle bits until erase completes or erase is suspended another time data 30h mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc.
m59mr032c, m59mr032d 20/49 status register bits p/e.c. status is indicated during execution by data polling on adq7, detection of toggle on adq6 and adq2, or error on adq5 bits. any read at- tempt within the bank being modified and during program or erase command execution will auto- matically output these five status register bits. the p/e.c. automatically sets bits adq2, adq5, adq6 and adq7. other bits (adq0, adq1 and adq4) are reserved for future use and should be masked (see table 18). read attempts within the bank not being modified will output array data. toggle bits adq6 and adq2 are affected by g and/or e cycles regardless of the bank in which these cycles refer to. this means that toggle bits are in a state that depends on the amount of ac- cesses to both banks and not only to the bank where erasing or programming is on going. status register bits must be accessed according to the device configuration (see figure 4). data polling bit (adq7). when programming operations are in progress, this bit outputs the complement of the bit being programmed on adq7. in case of a double word program opera- tion, the complement is done on adq7 of the last word written to the command interface, i.e. the data written in the fifth cycle. during erase opera- tion, it outputs a '0'. after completion of the opera- tion, adq7 will output the bit last programmed or a '1' after erasing. data polling is valid and only ef- fective during p/e.c. operation, that is after the fourth w pulse for programming or after the sixth w pulse for erase. it must be performed at the ad- dress being programmed or at an address within the block being erased. see figure 17 for the data polling flowchart and figure 15 for the data polling waveforms. adq7 will also flag the erase sus- pend mode by switching from '0' to '1' at the start of the erase suspend. in order to monitor adq7 in the erase suspend mode an address within a block being erased must be provided. for a read operation in suspend mode, adq7 will output '1' if the read is attempted on a block being erased and the data value on other blocks. during pro- gram operation in erase suspend mode, adq7 will have the same behavior as in the normal pro- gram execution outside of the suspend mode. toggle bit (adq6). when programming or eras- ing operations are in progress, successive at- tempts to read adq6 will output complementary data. adq6 will toggle following toggling of either g , or e when g is at v il . the operation is complet- ed when two successive reads yield the same out- put data. the next read will output the bit last programmed or a '1' after erasing. the toggle bit adq6 is valid only during p/e.c. operations, that is after the fourth w pulse for programming or after the sixth w pulse for erase. adq6 will be set to '1' if a read operation is attempted on an erase sus- pend block. when erase is suspended adq6 will toggle during programming operations in a block different from the block in erase suspend. either e or g toggling will cause adq6 to toggle. see figure 18 for toggle bit flowchart and figure 16 for toggle bit waveforms. toggle bit (adq2). this toggle bit, together with adq6, can be used to determine the device status during the erase operations. during erase sus- pend a read from a block being erased will cause adq2 to toggle. a read from a block not being erased will output data. adq2 will be set to '1' dur- ing program operation. after erase completion and if the error bit adq5 is set to '1', adq2 will toggle if the faulty block is addressed. error bit (adq5). this bit is set to '1' by the p/ e.c. when there is a failure of programming or block erase, that results in invalid data in the mem- ory block. in case of an error in block erase or pro- gram, the block in which the error occurred or to which the programmed data belongs, must be dis- carded. other blocks may still be used. the error bit resets after a read/reset (rd) instruction. in case of success of program or erase, the error bit will be set to '0'. erase timer bit (adq3). this bit is set to 0 by the p/e.c. when the last block erase command has been entered to the command interface and it is awaiting the erase start. when the erase time- out period is finished, adq3 returns to 1, in the range of 80s to 120s.
21/49 m59mr032c, m59mr032d table 18. status register bits (1) note: 1. status register bits do not consider binv. 2. dq7 and dq2 require a valid address when reading status information. status dq7 (2) dq6 dq5 dq3 dq2 (2) in progress program dq7 toggle 0 n/a 1 block erase timeout 0 toggle 0 0 n/a block/chip erase 0 toggle 0 1 n/a erase suspend mode erase suspended block 1 1 0 n/a toggle non erase suspended block automatic return to reading array data programming during erase suspend dq7 toggle 0 n/a 1 successfully/ completed word program automatic return to reading array data block/chip erase exceeded time limit word program dq7 toggle 1 n/a 1 block/chip erase 0 toggle 1 1 toggle is failed, block is addressed program in suspend dq7 toggle 1 n/a 1 power consumption power-down the memory provides reset/power-down control input rp . the power-down function can be acti- vated only if the relevant configuration register bit is set to '1'. in this case, when the rp signal is pulled at v ss the supply current drops to typically i cc2 (see table 28), the memory is deselected and the outputs are in high impedance.if rp is pulled to v ss during a program or erase operation, this operation is aborted in t plq7v and the memory content is no longer valid (see reset/power-down input description). power-up the memory command interface is reset on pow- er-up to read array. either e or w must be tied to v ih during power-up to allow maximum security and the possibility to write a command on the first rising edge of w . at power-up the device is config- ured as: C page mode: (cr15 = 1) C power-down disabled: (cr10 = 0) C binv disabled: (cr14 = 0) and all blocks are protected and unlocked. supply rails normal precautions must be taken for supply volt- age decoupling; each device in a system should have the v dd rails decoupled with a 0.1f capac- itor close to the v dd , v ddq and v ss pins. the pcb trace widths should be sufficient to carry the re- quired v dd program and erase currents.
m59mr032c, m59mr032d 22/49 table 19. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-se ctions detailed in tables 20, 21 and 22. query data are always presented on the lowest order data outputs. table 20. cfi query identification string note: query data are always presented on the lowest - order data outputs (adq0-adq7) only. adq8-adq15 are 0. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) offset data description 00h 0020h manufacturer code 01h 00a4h - top 00a5h - bottom device code 02h-0fh reserved reserved 10h 0051h query unique ascii string "qry" 11h 0052h 12h 0059h 13h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0039h address for primary algorithm extended query table 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (note: 0000h means none exists) 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table note: 0000h means none exists 1ah 0000h common flash interface (cfi) the common flash interface (cfi) specification is a jedec approved, standardised data structure that can be read from the flash memory device. cfi allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. cfi allows the system to easily interface to the flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. tables 19, 20, 21, 22, 23 and 24 show the address used to retrieve each data. the cfi data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. tables 19, 20, 21 and 22 show the addresses used to retrieve each data. the cfi data structure contains also a security area; in this section, a 64 bit unique secu- rity number is written, starting at address 81h. this area can be accessed only in read mode and there are no ways of changing the code after it has been written by st. write a read instruction to return to read mode. refer to the cfi query instruction to understand how the m59mr032 enters the cfi query mode.
23/49 m59mr032c, m59mr032d table 21. cfi query system interface information offset data description 1bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1ch 0022h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1dh 0017h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts note: this value must be 0000h if no v pp pin is present 1eh 00c0h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts note: this value must be 0000h if no v pp pin is present 1fh 0004h typical timeout per single byte/word program (multi-byte program count = 1), 2 n s (if supported; 0000h = not supported) 20h 0004h typical timeout for maximum-size multi-byte program or page write, 2 n s (if supported; 0000h = not supported) 21h 000ah typical timeout per individual block erase, 2 n ms (if supported; 0000h = not supported) 22h 0000h typical timeout for full chip erase, 2 n ms (if supported; 0000h = not supported) 23h 0004h maximum timeout for byte/word program, 2 n times typical (offset 1fh) (0000h = not supported) 24h 0004h maximum timeout for multi-byte program or page write, 2 n times typical (offset 20h) (0000h = not supported) 25h 0004h maximum timeout per individual block erase, 2 n times typical (offset 21h) (0000h = not supported) 26h 0000h maximum timeout for chip erase, 2 n times typical (offset 22h) (0000h = not supported)
m59mr032c, m59mr032d 24/49 table 22. device geometry definition offset word mode data description 27h 0016h device size = 2 n in number of bytes 28h 0001h flash device interface code description: asynchronous x16 29h 0000h 2ah 0000h maximum number of bytes in multi-byte program or page = 2 n 2bh 0000h 2ch 0003h number of erase block regions within device bit 7 to 0 = x = number of erase block regions note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more contiguous erase blocks of the same size. for example, a 128kb device (1mb) having blocking of 16kb, 8kb, four 2kb, two 16kb, and one 64kb is considered to have 5 erase block regions. even though two regions both contain 16kb blocks, the fact that they are not contiguous means they are sep- arate erase block regions. 3. by definition, symmetrically block devices have only one blocking region. m59mr032c m59mr032c erase block region information bit 31 to 16 = z, where the erase block(s) within this region are (z) times 256 bytes in size. the value z = 0 is used for 128 byte block size. e.g. for 64kb block size, z = 0100h = 256 => 256 * 256 = 64k bit 15 to 0 = y, where y+1 = number of erase blocks of identical size within the erase block region: e.g. y = d15-d0 = ffffh => y+1 = 64k blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 2dh 002fh 2eh 0000h 2fh 0000h 30h 0001h 31h 000eh 32h 0000h 33h 0000h 34h 0001h 35h 0007h 36h 0000h 37h 0020h 38h 0000h m59mr032d m59mr032d 2dh 0007h 2eh 0000h 2fh 0020h 30h 0000h 31h 000eh 32h 0000h 33h 0000h 34h 0001h 35h 002fh 36h 0000h 37h 0000h 38h 0001h
25/49 m59mr032c, m59mr032d table 23. primary algorithm-specific extended query table offset data description (p)h = 39h 0050h primary algorithm extended query table unique ascii string pri 0052h 0049h (p+3)h = 3ch 0031h major version number, ascii (p+4)h = 3dh 0030h minor version number, ascii (p+5)h = 3eh 00f2h extended query table contents for primary algorithm bit 10-31 reserved; undefined bits are 0. if bit 31 is 1 then another 31 bit field of optional features follows at the end of the bit-30 field. bit 0 chip erase supported (1 = yes, 0 = no) bit 1 suspend erase supported (1 = yes, 0 = no) bit 2 suspend program supported (1 = yes, 0 = no) bit 3 legacy lock/unlock supported (1 = yes, 0 = no) bit 4 queued erase supported (1 = yes, 0 = no) bit 5 instant individual block locking supported (1 = yes, 0 = no) bit 6 protection bits supported (1 = yes, 0 = no) bit 7 page-mode read supported (1 = yes, 0 = no) bit 8 synchronous read supported (1 = yes, 0 = no) bit 9 simultaneous operation supported (1 = yes, 0 = no) 0003h (p+7)h 0000h (p+8)h 0000h (p+9)h = 42h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are 0 (p+a)h = 43h 0003h block protect status defines which bits in the block protect status register section of the query are implemented. bit 0 block protect status register protect/unprotect bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are 0 (p+b)h 0000h (p+c)h = 45h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv (p+d)h = 46h 00c0h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv (p+e)h = 47h 0000h reserved
m59mr032c, m59mr032d 26/49 table 24. burst read information table 25. security code area offset data description (p+f)h = 48h 0003h page-mode read capability bits 0-7 n such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page- mode data output width. 00h indicates no read page buffer. (p+10)h = 49h 0003h number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. (p+11)h = 4ah 0001h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 n such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the devices burstable address space. this fields 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. (p+12)h = 4bh 0002h synchronous mode read capability configuration 2 (p+13)h = 4ch 0007h synchronous mode read capability configuration 3 (p+14)h = 4dh 0036h max operating clock frequency (mhz) (p+15)h = 4eh 0001h supported handshaking signal (wait pin) bit 0 during synchronous read (1 = yes, 0 = no) bit 1 during asynchronous read (1 = yes, 0 = no) offset data description 81h xxxx 64 bits: unique device number 82h xxxx 83h xxxx 84h xxxx
27/49 m59mr032c, m59mr032d figure 7. ac testing load circuit ai90115 v ddq / 2 out c l = 30pf c l includes jig capacitance 3.3k w 1n914 device under test table 26. ac measurement conditions input rise and fall times 4ns input pulse voltages 0 to v ddq input and output timing ref. voltages v ddq /2 figure 6. testing input/output waveforms ai90114 v ddq 0v v ddq /2 table 27. capacitance (1) (t a = 25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf
m59mr032c, m59mr032d 28/49 table 28. dc characteristics (t a = C40 to 85c; v dd = v ddq = 1.65v to 2.0v) note: 1. sampled only, not 100% tested. 2. v pp may be connected to 12v power supply for a total of less than 100 hrs. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 5 a i cc1 supply current (asynchronous read mode) e = v il , g = v ih , f = 6mhz 10 20 ma supply current (synchronous read mode continuous burst) e = v il , g = v ih , f = 40mhz 20 30 ma i cc2 supply current (power-down) rp = v ss 0.2v 210a i cc3 supply current (standby) e = v dd 0.2v 15 50 a i cc4 (1) supply current (program or erase) word program, block erase in progress 10 20 ma i cc5 (1) supply current (dual bank) program/erase in progress in one bank, asynchronous read in the other bank 20 40 ma program/erase in progress in one bank, synchronous read in the other bank 30 50 ma i pp1 v pp supply current (program or erase) v pp = 12v 0.6v 510ma i pp2 v pp supply current (standby or read) v pp v cc 0.2 5 a v pp = 12v 0.6v 100 400 a v il input low voltage C0.5 0.4 v v ih input high voltage v ddq C0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage cmos i oh = C100a v ddq C0.1 v v pp1 v pp supply voltage program, erase v ddq C0.4 v ddq + 0.4 v v pp2 v pp supply voltage double word program 11.4 12.6 v
29/49 m59mr032c, m59mr032d table 29. asynchronous read ac characteristics (t a = C40 to 85c; v dd = v ddq = 1.65v to 2.0v) note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . symbol alt parameter test condition m59mr032 unit 100 120 min max min max t avav t rc address valid to next address valid e = v il , g = v il 100 120 ns t avlh t avavdh address valid to latch enable high g = v ih 10 10 ns t av qv t acc address valid to output valid (random) e = v il , g = v il 100 120 ns t av qv 1 t pa ge address valid to output valid (page) e = v il , g = v il 45 45 ns t ehqx t oh chip enable high to output transition g = v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 20 20 ns t ellh t elavdh chip enable low to latch enable high e = v il , g = v ih 10 10 ns t elqv (2) t ce chip enable low to output valid g = v il 100 120 ns t elqx (1) t lz chip enable low to output transition g = v il 00ns t ghqx t oh output enable high to output transition e = v il 00ns t ghqz (1) t df output enable high to output hi-z e = v il 20 20 ns t glqv (2) t oe output enable low to output valid e = v il 25 35 ns t glqx (1) t olz output enable low to output transition e = v il 00ns t lhax t avd hax latch enable high to address transition e = v il , g = v ih 10 10 ns t lhgl latch enable high to output enable low e = v il 10 10 ns t lllh t avdlavdh latch enable pulse width e = v il , g = v ih 10 10 ns t llqv t avdlqv latch enable low to output valid (random) e = v il 100 120 ns t llqv1 latch enable low to output valid (page) e = v il 45 45 ns
m59mr032c, m59mr032d 30/49 figure 8. asynchronous read ac waveforms ai90116 tavav tavqv telqx tehqx tglqv tglqx tghqx adq0-adq15 e g telqv valid address tehqz tghqz valid data valid address a16-a20 valid address valid address l tellh tllqv tlllh tavlh tlhax tlhgl note: write enable (w ) = high.
31/49 m59mr032c, m59mr032d figure 9. page read ac waveforms ai90117 tavqv1 tglqv tghqz adq0-adq15 e g telqv valid address a16-a20 valid address l tllqv valid address valid data valid address valid data valid data valid address valid data tllqv1 tavlh tlhax tlhgl
m59mr032c, m59mr032d 32/49 table 30. synchronous burst read ac characteristics (t a = C40 to 85c; v dd = v ddq = 1.65v to 2.0v) symbol alt parameter test condition m59mr032 unit 100 120 min max min max t avk t avclkh address valid to clock 7 7 ns t elk t celclkh chip enable low to clock 7 7 ns t k t clk clock period 15 16 ns t kax t clkhax clock to address transition e = v il , g = v ih 10 10 ns t khkl t clkhclkl clock high 5 5 ns t klkh t clklclkh clock low 5 5 ns t krv t rlclkh clock to wait valid e = v il , g = v il 14 18 ns t krx t clkhrx clock to wait transition e = v il , g = v il 44ns t kqv t clkhqv clock to data valid e = v il , g = v il 14 18 ns t kqx t clkhqx clock to output transition e = v il 44ns t llk t avdlclkh latch enable low to clock 7 7 ns
33/49 m59mr032c, m59mr032d figure 10. synchronous burst read ai90118 adq0-adq15 e g a16-a20 l binv wait k valid address valid d. valid d. valid valid address tlhax tavlh tglqx tavk tllk telk tkax tlhgl tkqx tkqv valid data valid d. valid valid note 1 note 2 note 3 tkrv tkrv tehqx tehqz tghqx tghqz note: 1. the number of clock cycles to be inserted depends upon the x-latency set in the read configuration register. 2. wait signal can be configured to be active during wait state or one cycle below wait state. 3. wait signal is asserted only when burst length is configured as continuous (see burst read section for further information).
m59mr032c, m59mr032d 34/49 figure 11. synchronous burst read (with data hold configuration bit cr9 = 1) ai90119 adq0-adq15 e g a16-a20 l binv wait k valid data valid data valid data valid valid valid note 1 note 2 note: 1. wait signal can be configured to be active during wait state or one cycle below wait state. 2. wait signal is asserted only when burst length is configured as continuous (see burst read section for further information).
35/49 m59mr032c, m59mr032d table 31. write ac characteristics, write enable controlled (t a = C40 to 85 c; v dd = v ddq = 1.65v to 2.0v) symbol alt parameter m59mr032 unit 100 120 min max min max t avav t wc address valid to next address valid 100 120 ns t avlh address valid to latch enable high 10 10 ns t dvwh t ds input valid to write enable high 50 50 ns t ellh chip enable low to latch enable high 10 10 ns t elwl t cs chip enable low to write enable low 0 0 ns t ghll output enable high to latch enable low 20 20 ns t ghwl output enable high to write enable low 20 20 ns t lhax latch enable high to address transition 10 10 ns t lhwh latch enable high to write enable high 10 10 ns t lllh latch enable pulse width 10 10 ns t plq7v rp low to reset complete during program/erase 15 15 s t vdhel t vcs v dd high to chip enable low 50 50 s t vpphwh v pp high to write enable high 200 200 ns t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whgl t oeh write enable high to output enable low 0 0 ns t whll write enable high to latch enable low 0 0 ns t whvppl write enable high to v pp low 200 200 ns t whwl t wph write enable high to write enable low 30 30 ns t whwpl write enable high to write protect low 200 200 ns t wlwh t wp write enable low to write enable high 50 50 ns t wphwh write protect high to write enable high 200 200 ns
m59mr032c, m59mr032d 36/49 figure 12. write ac waveforms, w controlled ai90120 tlhax adq0-adq15 l g tavlh data valid address valid a16-a20 e tlllh telwl tghwl w address valid tdvwh twhdx twlwh tellh tghll twhgl v dd tvdhel binv valid tlhwh twhll wp twphwh twhwpl v pp tvpphwh v pp1 v pp2 twhvppl tavav
37/49 m59mr032c, m59mr032d table 32. write ac characteristics, chip enable controlled (t a = C40 to 85 c; v dd = v ddq = 1.65v to 2.0v) symbol alt parameter m59mr032 unit 100 120 min max min max t avav t wc address valid to next address valid 100 120 ns t avlh address valid to latch enable high 10 10 ns t dveh t ds input valid to chip enable high 50 50 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 ns t ehwh t wh chip enable high to write enable high 0 0 ns t eleh t cp chip enable low to chip enable high 70 70 ns t ellh chip enable low to latch enable high 10 10 ns t ghll output enable high to latch enable low 20 20 ns t lhax latch enable high to address transition 10 10 ns t lheh latch enable high to chip enable high 10 10 ns t lllh latch enable pulse width 10 10 ns t plq7v rp low to reset complete during program/erase 15 15 s t vdhwl t vcs v dd high to write enable low 50 50 s t vppheh v pp high to chip enable high 200 200 ns t ehvppl chip enable high to v pp low 200 200 ns t ehwpl chip enable high to write protect low 200 200 ns t wlel t ws write enable low to chip enable low 0 0 ns t wpheh write protect high to chip enable high 200 200 ns
m59mr032c, m59mr032d 38/49 figure 13. write ac waveforms, e controlled tlhax adq0-adq15 l g tavlh data valid address valid a16-a20 e tlllh teleh w address valid tdveh tehdx tehwh tellh tghll binv valid tlheh twlel ai90121 v dd tvdhwl wp twpheh tehwpl v pp tvppheh v pp1 v pp2 tehvppl tavav tehel
39/49 m59mr032c, m59mr032d figure 14. read and write ac waveforms, rp related ai90122 adq7 w rp tplph tphq7v1,2 valid read adq7 valid tplq7v program / erase table 33. read and write ac characteristic, rp related (t a = C40 to 85c; v dd = v ddq = 1.65v to 2.0v) symbol alt parameter test condition m59mr032 unit 100 120 min max min max t phq7v1 rp high to data valid (read mode) 150 150 ns t phq7v2 rp high to data valid (power-down enabled) 50 50 s t plph t rp rp pulse width 100 100 ns t plq7v rp low to reset complete during program/erase 15 15 s
m59mr032c, m59mr032d 40/49 table 34. program, erase times and program, erase endurance cycles (t a = 0 to 70c; v dd = v ddq = 1.65v to 2.0v, v pp = v dd unless otherwise specified) note: 1. max values refer to the maximum time allowed by the internal algorithm before error bit is set. worst case conditions pr ogram or erase should perform significantly better. 2. excludes the time needed to execute the sequence for program instruction. 3. same timing value if v pp = 12v . table 35. data polling and toggle bits ac characteristics (1) (t a = C40 to 85 c; v dd = v ddq = 1.65v to 2.0v) note: 1. all other timings are defined in read ac characteristics table. parameter min max (1) typ typical after 100k w/e cycles unit parameter block (4 kword) erase (preprogrammed) 2.5 0.15 0.4 sec main block (32 kword) erase (preprogrammed) 10 1 3 sec bank erase (preprogrammed, bank a) 2 6 sec bank erase (preprogrammed, bank b) 10 30 sec chip program (2) 20 25 sec chip program (dpg, v pp = 12v) (2) 10 sec word program (3) 200 10 10 s double word program 200 10 10 s program/erase cycles (per block) 100,000 cycles symbol parameter min max unit t ehq7v chip enable high to dq7 valid (program, e controlled) 10 200 s chip enable high to dq7 valid (block erase, e controlled) 1.0 10 sec t ehqv chip enable high to output valid (program) 10 200 s chip enable high to output valid (block erase) 1.0 10 sec t q7vqv q7 valid to output valid (data polling) 0 ns t whq7v write enable high to dq7 valid (program, w controlled) 10 200 s write enable high to dq7 valid (block erase, w controlled) 1.0 10 sec t whqv write enable high to output valid (program) 10 200 s write enable high to output valid (block erase) 1.0 10 sec
41/49 m59mr032c, m59mr032d figure 15. data polling adq7 ac waveforms (when configuration register bit cr15 = 1) ai90123 e g w adq7 ignore valid adq0-adq6/ adq8-adq15 tglqv twhq7v valid tq7vqv dq7 data polling read cycle data phase of last write cycle of program or erase instruction telqv tehq7v note: latch enable (l ) = high.
m59mr032c, m59mr032d 42/49 figure 16. data toggle dq6, dq2 ac waveforms (when configuration register bit cr15 = 1) ai90124 e g w adq6,adq2 stop toggle data phase of last write cycle of program of erase instruction valid data toggle read cycle twhqv tglqv toggle toggle
43/49 m59mr032c, m59mr032d figure 17. data polling flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai90125 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no figure 18. data toggle flowchart read dq5 & dq6 start read dq6 fail pass ai90126 dq6 = toggles no no yes yes dq5 = 1 no yes dq6 = toggles
m59mr032c, m59mr032d 44/49 table 36. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. table 37. daisy chain ordering scheme for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m59mr032c 100 gc 6 t device type m59 architecture m = multiplexed address/data, dual bank, burst mode operating voltage r = 1.8v device function 032c = 32 mbit (x16), dual bank: 1/4-3/4 partitioning, top boot 032d = 32 mbit (x16), dual bank: 1/4-3/4 partitioning, bottom boot speed 100 = 100 ns 120 = 120 ns package zc = lfbga54: 0.5 mm pitch gc = bga46: 0.5 mm pitch temperature range 6 = C40 to 85c option t = tape & reel packing example: m59mr032 -gc t device type m59mr032 daisy chain -gc = bga46: 0.5 mm pitch option t = tape & reel packing
45/49 m59mr032c, m59mr032d table 38. revision history date version revision details july 1999 -01 first issue 12/01/99 -02 fbga connections change fbga package mechanical data and outline change fbga daisy chain diagrams added bga package added 3/23/00 -03 document type: from product preview to preliminary data bus invert (binv) configuration bit clarification read operations clarification status register clarification lfbga package mechanical data change bga package mechanical data change 5/17/00 -04 bga package mechanical data change 9/26/00 -05 cfi primary algorithm modified cfi burst read modified write ac waveforms diagrams change (figure 12, 13) 12/20/00 -06 document type: from preliminary data to data sheet lfbga connection change (figure 2) bga connection change (figure 3) program time clarification (table 33) lfbga package mechanical data and outline change (table 39, figure 19) bga package mechanical data and outline change (table 40, figure 20) 3/02/01 -07 bga package mechanical data and outline change (table 40, figure 20) 3/19/01 -08 bga package mechanical data change (table 40)
m59mr032c, m59mr032d 46/49 table 39. lfbga54 - 10 x 4 ball array, 0.5 mm pitch, package mechanical data millimeters inches symbol typ min max typ min max a 1.100 1.000 1.200 0.0433 0.0394 0.0472 a1 0.150 0.100 0.250 0.0059 0.0039 0.0098 a2 0.950 C C 0.0374 C C b 0.400 0.300 0.450 0.0157 0.0118 0.0177 d 7.000 6.800 7.200 0.2756 0.2677 0.2835 d1 4.500 C C 0.1772 C C ddd 0.150 0.0059 e 0.500 C C 0.0197 C C e 12.000 11.800 12.200 0.4724 0.4646 0.4803 e1 1.500 C C 0.0591 C C e2 6.500 C C 0.2559 C C e3 1.000 C C 0.0394 C C e4 0.500 C C 0.0197 C C fd 1.250 C C 0.0492 C C fe 5.250 C C 0.2067 C C sd 0.250 C C 0.0098 C C se 0.250 C C 0.0098 C C figure 19. lfbga54 - 10 x 4 ball array, 0.5 mm pitch, bottom view package outline drawing is not to scale. e1 e d eb sd se a2 a1 a bga-z06 ddd e2 dummy balls ball "a1" d1 e4 e3 fe fd
47/49 m59mr032c, m59mr032d table 40. bga46 - 10 x 4 ball array, 0.5 mm pitch, package mechanical data millimeters inches symbol typ min max typ min max a 1.000 0.0394 a1 0.150 0.0059 a2 0.700 0.0276 b 0.320 0.250 0.400 0.0126 0.0098 0.0157 d 10.530 10.480 10.580 0.4146 0.4126 0.4165 d1 4.500 C C 0.1772 C C d2 6.500 C C 0.2559 C C d3 8.500 C C 0.3346 C C ddd 0.080 0.0031 e 0.500 C C 0.0197 C C e 6.290 6.240 6.340 0.2476 0.2457 0.2496 e1 1.500 C C 0.0591 C C e2 3.500 C C 0.1378 C C e3 5.500 C C 0.2165 C C fd 3.015 C C 0.1187 C C fd1 2.015 C C 0.0793 C C fd2 1.015 C C 0.0400 C C fe 2.395 C C 0.0943 C C fe1 1.395 C C 0.0549 C C fe2 0.395 C C 0.0156 C C sd 0.250 C C 0.0098 C C se 0.250 C C 0.0098 C C figure 20. bga46 - 10 x 4 ball array, 0.5 mm pitch, bottom view package outline drawing is not to scale. a2 a1 bga-g07 dummy balls d d1 e fd2 fd1 b e e1 ddd e3 d3 sd se fe a ball "a1" e2 d2 fd fe1 fe2
m59mr032c, m59mr032d 48/49 figure 21. bga46 daisy chain - package connections (top view through package) figure 22. bga46 daisy chain - pcb connections proposal (top view through package) ai90127 h g 6 5 4 3 d c e f a b 12 78 13 12 11 10 914 end point start point ai90128 h g 6 5 4 3 d c e f a b 12 78 13 12 11 10 914
49/49 m59mr032c, m59mr032d information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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